Master FPGA Design: Build an Alarm Clock with VHDL (2024)
Focused View
2:03:27
1 -Introduction.mp4
01:38
2 -Specification.mp4
07:24
1 -Material used.mp4
04:33
2 -Mimas V2 FPGA board.mp4
03:36
3 -Buzzer.mp4
04:07
4 -4 digits 7 segments display.mp4
12:12
5 -Breadboard.mp4
04:45
1 -InputOutput ports.mp4
02:38
2 -Debounce button.mp4
06:01
3 -Clock divider.mp4
11:01
4 -Counters.mp4
12:03
5 -Binary to BCD.mp4
11:45
6 -Buzzer controller.mp4
08:27
7 -Display controller.mp4
08:45
8 -Alarm clock.mp4
03:12
1 -Simulation.mp4
15:01
3 -Synthesis.mp4
01:28
4 -Demonstration.mp4
04:06
4 -alarm clock.zip
4 -bin2bcd.zip
4 -clock mult div.zip
4 -constraints.zip
4 -debounce button.zip
4 -tb alarm clock.zip
1 -Final words.mp4
00:45
More details
Course Overview
This hands-on course teaches practical FPGA design by guiding you through building a functional alarm clock from concept to hardware implementation using VHDL and FPGA boards.
What You'll Learn
- Digital logic design with VHDL for FPGAs
- Interfacing with 7-segment displays and buzzers
- FPGA synthesis, simulation, and hardware testing
Who This Is For
- Beginner digital electronics students
- Engineers learning FPGA development
- Hobbyists interested in hardware design
Key Benefits
- Practical project-based learning approach
- Complete system from design to demonstration
- Real-world skills in VHDL and FPGA toolchains
Curriculum Highlights
- FPGA project specification and materials
- VHDL implementation of alarm clock
- Testing and synthesis on FPGA hardware
Focused display
Category
- language english
- Training sessions 19
- duration 2:03:27
- Release Date 2025/04/26